WILMINGTON, DE — Qnity Electronics, Inc. (NYSE: Q) introduced new advanced packaging materials aimed at semiconductor manufacturers building next-generation artificial intelligence processors, expanding its portfolio for organic interposers, redistribution layers and emerging glass-substrate packaging architectures.
The product launch targets a critical area of the semiconductor industry as AI-driven computing demands increase pressure on chipmakers to improve interconnect density, performance and manufacturing reliability through advanced packaging technologies.
Qnity said its new offerings include Intervia 8540HSP copper, a metallization material designed for micro-bump and copper redistribution layer applications, and Cyclotene DF6800M, a dry-film photo-imageable dielectric intended for glass-core substrates and glass interposers.
The company said Intervia 8540HSP is engineered for advanced packaging applications used in AI-focused graphics processing units, providing high-purity copper deposition and uniformity characteristics intended to support fine-pitch interconnect formation.
Cyclotene DF6800M is designed to support multilayer semiconductor packaging structures, including glass-based substrate designs that are attracting increased industry interest as chipmakers seek alternatives for higher-density packaging and advanced interconnect configurations.
“AI is fundamentally changing how chips are packaged—and materials have to evolve just as fast,” said Chuck Xu, president of Interconnect Solutions at Qnity. “As architectures move from shrinking to stacking, we’re focused on enabling that shift with advanced materials that give our customers a clear edge in performance, yield, and long-term reliability.”
The launch expands Qnity’s advanced packaging materials portfolio as semiconductor manufacturers invest in technologies supporting wafer-level packaging, panel-level packaging and other approaches intended to improve performance and power efficiency in AI and high-performance computing applications.
Advanced packaging has become an increasingly important competitive focus across the semiconductor industry as gains from traditional transistor scaling become more difficult to achieve and manufacturers turn to chiplet-based and multi-die architectures to improve computing performance.
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