Qnity Targets AI Chip Packaging With Integrated Materials

Qnity Electronics

WILMINGTON, DE — Qnity Electronics Inc. (NYSE: Q) introduced an integrated semiconductor-materials platform at SEMICON Taiwan on Sept. 1, targeting the manufacturing complexity created by artificial intelligence chips, high-bandwidth memory and stacked architectures.

The platform combines materials for metallization, micro-bump formation, dielectric insulation and fine-line patterning. Qnity designed the portfolio for 2.5D, 3D and panel-level packaging, which connect multiple chips within increasingly dense systems.

Those packaging methods are becoming more important as manufacturers combine chiplets, memory and other components rather than relying solely on traditional two-dimensional designs. Their performance depends partly on producing smaller, more uniform connections while limiting manufacturing defects.

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Qnity said its materials can support metallization with lines and spaces as narrow as 2 micrometers. The portfolio also covers tin-silver micro-bumps, copper-to-copper direct and hybrid bonding and high-resolution patterning.

“As AI, chiplets, high-bandwidth memory, 3D stacking, and heterogeneous integration drive a shift from 2D designs to increasingly complex vertical architectures, semiconductor manufacturers are facing new levels of integration complexity,” Chuck Xu, president of Qnity’s Interconnect Solutions business, said.

The company is positioning the combined portfolio for packaging systems including Chip-on-Wafer-on-Substrate, Embedded Multi-die Interconnect Bridge and high-bandwidth memory. Such applications require precise plating heights and level surfaces to maintain reliable connections among components.

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Among the products is Intervia CB1000+ and CB3000 copper, designed to control copper-deposition uniformity and impurities within individual dies.

Qnity’s Solderon TS8000 series uses tin-silver plating for high-bandwidth-memory micro-bumps. The material supports different bump sizes and spacing patterns with soluble or insoluble electrode-plating systems.

The portfolio also includes Riston WBR5000, a dry-film photoresist for 2.5D packaging. Available in thicknesses from 200 to 320 micrometers, the material is intended for copper-pillar plating and fine-feature lithography.

Cyclotene, a photo-imageable dielectric film, targets fan-out panel-level packaging and advanced substrates. For glass-core substrates, it can fill through-glass vias, which carry electrical connections through the material.

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Qnity detailed the platform during the Heterogeneous Integration Global Summit at SEMICON Taiwan 2026. Jason Chuang, the company’s packaging polymer segment director for advanced circuit and packaging, delivered the presentation.

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